; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d]
; commandline ArmCC [--c99 --list --split_sections --debug -c --asm --interleave -o..\output\sc32f1xxx_pwr.o --asm_dir=..\List\ --list_dir=..\List\ --depend=..\output\sc32f1xxx_pwr.d --cpu=Cortex-M0+ --apcs=interwork --diag_suppress=9931 -I..\FWLib\SC32F1XXX_Lib\inc -I..\User\HeadFiles -I..\User -I..\Drivers -I..\Apps -I..\CMSIS -IF:\Users\SOC\AppData\Local\Arm\Packs\ARM\CMSIS\5.8.0\Device\ARM\ARMCM0plus\Include -D__UVISION_VERSION=536 -DARMCM0P -DSC32f10xx --omf_browse=..\output\sc32f1xxx_pwr.crf ..\FWLib\SC32F1XXX_Lib\src\sc32f1xxx_pwr.c]
                          THUMB

                          AREA ||i.PWR_EnterIDLEMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterIDLEMode PROC
;;;48       */
;;;49     void PWR_EnterIDLEMode ( uint8_t PWR_IDLEEntry )
000000  4906              LDR      r1,|L1.28|
;;;50     {
;;;51         /* Check the parameters */
;;;52         assert_param ( IS_PWR_IDLE_ENTRY ( PWR_IDLEEntry ) );
;;;53     
;;;54         /* Reset SLEEPDEEP bit of Cortex System Control Register */
;;;55         SCB->SCR &= ( uint32_t ) ~ ( ( uint32_t ) SCB_SCR_SLEEPDEEP_Msk );
000002  690a              LDR      r2,[r1,#0x10]
000004  2304              MOVS     r3,#4
000006  439a              BICS     r2,r2,r3
000008  610a              STR      r2,[r1,#0x10]
;;;56     
;;;57         /* Select SLEEP mode entry -------------------------------------------------*/
;;;58         if ( PWR_IDLEEntry == PWR_IDLEEntry_WFI )
00000a  2801              CMP      r0,#1
00000c  d003              BEQ      |L1.22|
;;;59         {
;;;60             /* Request Wait For Interrupt */
;;;61             __WFI();
;;;62         }
;;;63         else
;;;64         {
;;;65             /* Request Wait For Event */
;;;66             __SEV();
00000e  bf40              SEV      
;;;67             __WFE();
000010  bf20              WFE      
;;;68             __WFE();
000012  bf20              WFE      
;;;69         }
;;;70     }
000014  4770              BX       lr
                  |L1.22|
000016  bf30              WFI                            ;61
000018  4770              BX       lr
;;;71     
                          ENDP

00001a  0000              DCW      0x0000
                  |L1.28|
                          DCD      0xe000ed00

                          AREA ||i.PWR_EnterSTOPMode||, CODE, READONLY, ALIGN=2

                  PWR_EnterSTOPMode PROC
;;;80       */
;;;81     void PWR_EnterSTOPMode ( uint8_t PWR_STOPEntry )
000000  4907              LDR      r1,|L2.32|
;;;82     {
;;;83         /* Check the parameters */
;;;84         assert_param ( IS_PWR_STOP_ENTRY ( PWR_STOPEntry ) );
;;;85     
;;;86         /* Set STOPDEEP bit of Cortex System Control Register */
;;;87         SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
000002  690b              LDR      r3,[r1,#0x10]
000004  2204              MOVS     r2,#4
000006  4313              ORRS     r3,r3,r2
000008  610b              STR      r3,[r1,#0x10]
;;;88     
;;;89         /* Select STOP mode entry -------------------------------------------------*/
;;;90         if ( PWR_STOPEntry == PWR_STOPEntry_WFI )
00000a  2801              CMP      r0,#1
00000c  d006              BEQ      |L2.28|
;;;91         {
;;;92             /* Request Wait For Interrupt */
;;;93             __WFI();
;;;94         }
;;;95         else
;;;96         {
;;;97             /* Request Wait For Event */
;;;98             __SEV();
00000e  bf40              SEV      
;;;99             __WFE();
000010  bf20              WFE      
;;;100            __WFE();
000012  bf20              WFE      
                  |L2.20|
;;;101        }
;;;102    
;;;103        /* Reset STOPDEEP bit of Cortex System Control Register */
;;;104        SCB->SCR &= ( uint32_t ) ~ ( ( uint32_t ) SCB_SCR_SLEEPDEEP_Msk );
000014  6908              LDR      r0,[r1,#0x10]
000016  4390              BICS     r0,r0,r2
000018  6108              STR      r0,[r1,#0x10]
;;;105    }
00001a  4770              BX       lr
                  |L2.28|
00001c  bf30              WFI                            ;93
00001e  e7f9              B        |L2.20|
;;;106    
                          ENDP

                  |L2.32|
                          DCD      0xe000ed00

;*** Start embedded assembler ***

#line 1 "..\\FWLib\\SC32F1XXX_Lib\\src\\sc32f1xxx_pwr.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_sc32f1xxx_pwr_c_5fda2d5e____REV16|
#line 463 "..\\CMSIS\\cmsis_armcc.h"
|__asm___15_sc32f1xxx_pwr_c_5fda2d5e____REV16| PROC
#line 464

 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_sc32f1xxx_pwr_c_5fda2d5e____REVSH|
#line 478
|__asm___15_sc32f1xxx_pwr_c_5fda2d5e____REVSH| PROC
#line 479

 revsh r0, r0
 bx lr
	ENDP

;*** End   embedded assembler ***
