﻿; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: armcc [4d365d]
; commandline armcc [--c99 --list --split_sections --debug -c --asm --interleave -o..\Output\sc32f1xxx_tim.o --asm_dir=..\List --list_dir=..\List --cpu=Cortex-M0+ --apcs=interwork -I..\FWLib\SC32F1XXX_Lib\inc -I..\User\HeadFiles -I..\User -I..\Drivers -I..\Apps -I..\CMSIS -DSC32f12xx -D__UVISION_VERSION=536 ..\FWLib\SC32F1XXX_Lib\src\sc32f1xxx_tim.c]
                          THUMB
                          AREA ||i.TIM_ClearFlag||, CODE, READONLY, ALIGN=1
                  TIM_ClearFlag PROC
;;;995     */
;;;996    void TIM_ClearFlag ( TIM_TypeDef* TIMx, uint16_t TIM_FLAG )
000000  60c1              STR      r1,[r0,#0xc]
;;;997    {
;;;998        
;;;999        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;1000   
;;;1001       
;;;1002       TIMx->TIM_STS = ( uint16_t ) TIM_FLAG;
;;;1003   }
000002  4770              BX       lr
;;;1004   
                          ENDP
                          AREA ||i.TIM_ClockOutputCmd||, CODE, READONLY, ALIGN=1
                  TIM_ClockOutputCmd PROC
;;;807     */
;;;808    void TIM_ClockOutputCmd ( TIM_TypeDef* TIMx, FunctionalState NewState )
000000  2201              MOVS     r2,#1
;;;809    {
;;;810        
;;;811        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;812        assert_param ( IS_FUNCTIONAL_STATE ( NewState ) );
;;;813    
;;;814        if ( NewState != DISABLE )
;;;815        {
;;;816            
;;;817            TIMx->TIM_CON |= TIM_CON_TXOE;
000002  03d2              LSLS     r2,r2,#15
000004  2900              CMP      r1,#0                 ;814
;;;818        }
;;;819        else
;;;820        {
;;;821            
;;;822            TIMx->TIM_CON &= ( uint32_t ) ~TIM_CON_TXOE;
000006  6801              LDR      r1,[r0,#0]
000008  d001              BEQ      |L2.14|
00000a  4311              ORRS     r1,r1,r2              ;817
00000c  e000              B        |L2.16|
                  |L2.14|
00000e  4391              BICS     r1,r1,r2
                  |L2.16|
000010  6001              STR      r1,[r0,#0]            ;817
;;;823        }
;;;824    }
000012  4770              BX       lr
;;;825    
                          ENDP
                          AREA ||i.TIM_Cmd||, CODE, READONLY, ALIGN=2
                  TIM_Cmd PROC
;;;201     */
;;;202    void TIM_Cmd ( TIM_TypeDef* TIMx, FunctionalState NewState )
000000  2900              CMP      r1,#0
;;;203    {
;;;204        
;;;205        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;206        assert_param ( IS_FUNCTIONAL_STATE ( NewState ) );
;;;207    
;;;208        if ( NewState != DISABLE )
;;;209        {
;;;210            
;;;211            TIMx->TIM_CON |= TIM_CON_TR;
;;;212        }
;;;213        else
;;;214        {
;;;215            
;;;216            TIMx->TIM_CON &= ( uint16_t ) ~TIM_CON_TR;
000002  6801              LDR      r1,[r0,#0]
000004  d002              BEQ      |L3.12|
000006  2280              MOVS     r2,#0x80              ;211
000008  4311              ORRS     r1,r1,r2              ;211
00000a  e001              B        |L3.16|
                  |L3.12|
00000c  4a01              LDR      r2,|L3.20|
00000e  4011              ANDS     r1,r1,r2
                  |L3.16|
000010  6001              STR      r1,[r0,#0]            ;211
;;;217        }
;;;218    }
000012  4770              BX       lr
;;;219    
                          ENDP
                  |L3.20|
                          DCD      0x0000ff7f
                          AREA ||i.TIM_DMACmd||, CODE, READONLY, ALIGN=1
                  TIM_DMACmd PROC
;;;1028    */
;;;1029   void TIM_DMACmd ( TIM_TypeDef* TIMx, uint16_t TIM_DMAReq, FunctionalState NewState )
000000  2a00              CMP      r2,#0
;;;1030   {
;;;1031       
;;;1032       assert_param ( IS_TIM_DMA_PERIPH ( TIMx ) );
;;;1033       assert_param ( IS_FUNCTIONAL_STATE ( NewState ) );
;;;1034   
;;;1035       if ( NewState != DISABLE )
;;;1036       {
;;;1037           
;;;1038           TIMx->TIM_IDE |= TIM_DMAReq;
;;;1039       }
;;;1040       else
;;;1041       {
;;;1042           
;;;1043           TIMx->TIM_IDE &= ( uint16_t ) ~TIM_DMAReq;
000002  6982              LDR      r2,[r0,#0x18]
000004  d001              BEQ      |L4.10|
000006  430a              ORRS     r2,r2,r1              ;1038
000008  e002              B        |L4.16|
                  |L4.10|
00000a  43c9              MVNS     r1,r1
00000c  b289              UXTH     r1,r1
00000e  400a              ANDS     r2,r2,r1
                  |L4.16|
000010  6182              STR      r2,[r0,#0x18]         ;1038
;;;1044       }
;;;1045   }
000012  4770              BX       lr
;;;1046   
                          ENDP
                          AREA ||i.TIM_DeInit||, CODE, READONLY, ALIGN=2
                  TIM_DeInit PROC
;;;56      */
;;;57     void TIM_DeInit ( TIM_TypeDef* TIMx )
000000  492d              LDR      r1,|L5.184|
;;;58     {
000002  b510              PUSH     {r4,lr}
;;;59         assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;60     
;;;61         if ( TIMx == TIM0 )
000004  4288              CMP      r0,r1
000006  d106              BNE      |L5.22|
;;;62         {
;;;63             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM0, ENABLE );
000008  2101              MOVS     r1,#1
00000a  4608              MOV      r0,r1
00000c  f7fffffe          BL       RCC_APB0PeriphResetCmd
;;;64             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM0, DISABLE );
000010  2100              MOVS     r1,#0
000012  2001              MOVS     r0,#1
000014  e009              B        |L5.42|
                  |L5.22|
;;;65         }
;;;66         else if ( TIMx == TIM1 )
000016  4928              LDR      r1,|L5.184|
000018  3140              ADDS     r1,r1,#0x40
00001a  4288              CMP      r0,r1
00001c  d108              BNE      |L5.48|
;;;67         {
;;;68             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM1, ENABLE );
00001e  2101              MOVS     r1,#1
000020  2002              MOVS     r0,#2
000022  f7fffffe          BL       RCC_APB0PeriphResetCmd
;;;69             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM1, DISABLE );
000026  2100              MOVS     r1,#0
000028  2002              MOVS     r0,#2
                  |L5.42|
00002a  f7fffffe          BL       RCC_APB0PeriphResetCmd
;;;70         }
;;;71     #if !defined(SC32f15xx)
;;;72         else if ( TIMx == TIM2 )
;;;73         {
;;;74             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM2, ENABLE );
;;;75             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM2, DISABLE );
;;;76         }
;;;77     
;;;78         else if ( TIMx == TIM3 )
;;;79         {
;;;80             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM3, ENABLE );
;;;81             RCC_APB0PeriphResetCmd ( RCC_APB0Periph_TIM3, DISABLE );
;;;82         }
;;;83     #else
;;;84       else if(TIMx == TIM2)
;;;85       {
;;;86         RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
;;;87         RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
;;;88       }
;;;89       else if(TIMx == TIM3)
;;;90       {
;;;91         RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
;;;92         RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
;;;93       }
;;;94     #endif	
;;;95     #if !defined(SC32f15xx)
;;;96         else if ( TIMx == TIM4 )
;;;97         {
;;;98             RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM4, ENABLE );
;;;99             RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM4, DISABLE );
;;;100        }
;;;101        else if ( TIMx == TIM5 )
;;;102        {
;;;103            RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM5, ENABLE );
;;;104            RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM5, DISABLE );
;;;105        }
;;;106        else if ( TIMx == TIM6 )
;;;107        {
;;;108            RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM6, ENABLE );
;;;109            RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM6, DISABLE );
;;;110        }
;;;111        else if ( TIMx == TIM7 )
;;;112        {
;;;113            RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM7, ENABLE );
;;;114            RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM7, DISABLE );
;;;115        }
;;;116    #endif
;;;117    }
00002e  bd10              POP      {r4,pc}
                  |L5.48|
000030  4921              LDR      r1,|L5.184|
000032  3180              ADDS     r1,r1,#0x80           ;72
000034  4288              CMP      r0,r1                 ;72
000036  d106              BNE      |L5.70|
000038  2101              MOVS     r1,#1                 ;74
00003a  2004              MOVS     r0,#4                 ;74
00003c  f7fffffe          BL       RCC_APB0PeriphResetCmd
000040  2100              MOVS     r1,#0                 ;75
000042  2004              MOVS     r0,#4                 ;75
000044  e7f1              B        |L5.42|
                  |L5.70|
000046  491c              LDR      r1,|L5.184|
000048  31c0              ADDS     r1,r1,#0xc0           ;78
00004a  4288              CMP      r0,r1                 ;78
00004c  d106              BNE      |L5.92|
00004e  2101              MOVS     r1,#1                 ;80
000050  2008              MOVS     r0,#8                 ;80
000052  f7fffffe          BL       RCC_APB0PeriphResetCmd
000056  2100              MOVS     r1,#0                 ;81
000058  2008              MOVS     r0,#8                 ;81
00005a  e7e6              B        |L5.42|
                  |L5.92|
00005c  4917              LDR      r1,|L5.188|
00005e  4288              CMP      r0,r1                 ;96
000060  d106              BNE      |L5.112|
000062  2101              MOVS     r1,#1                 ;98
000064  4608              MOV      r0,r1                 ;98
000066  f7fffffe          BL       RCC_APB1PeriphResetCmd
00006a  2100              MOVS     r1,#0                 ;99
00006c  2001              MOVS     r0,#1                 ;99
00006e  e009              B        |L5.132|
                  |L5.112|
000070  4912              LDR      r1,|L5.188|
000072  3140              ADDS     r1,r1,#0x40           ;101
000074  4288              CMP      r0,r1                 ;101
000076  d108              BNE      |L5.138|
000078  2101              MOVS     r1,#1                 ;103
00007a  2002              MOVS     r0,#2                 ;103
00007c  f7fffffe          BL       RCC_APB1PeriphResetCmd
000080  2100              MOVS     r1,#0                 ;104
000082  2002              MOVS     r0,#2                 ;104
                  |L5.132|
000084  f7fffffe          BL       RCC_APB1PeriphResetCmd
                  |L5.136|
000088  bd10              POP      {r4,pc}
                  |L5.138|
00008a  490c              LDR      r1,|L5.188|
00008c  3180              ADDS     r1,r1,#0x80           ;106
00008e  4288              CMP      r0,r1                 ;106
000090  d106              BNE      |L5.160|
000092  2101              MOVS     r1,#1                 ;108
000094  2004              MOVS     r0,#4                 ;108
000096  f7fffffe          BL       RCC_APB1PeriphResetCmd
00009a  2100              MOVS     r1,#0                 ;109
00009c  2004              MOVS     r0,#4                 ;109
00009e  e7f1              B        |L5.132|
                  |L5.160|
0000a0  4906              LDR      r1,|L5.188|
0000a2  31c0              ADDS     r1,r1,#0xc0           ;111
0000a4  4288              CMP      r0,r1                 ;111
0000a6  d1ef              BNE      |L5.136|
0000a8  2101              MOVS     r1,#1                 ;113
0000aa  2008              MOVS     r0,#8                 ;113
0000ac  f7fffffe          BL       RCC_APB1PeriphResetCmd
0000b0  2100              MOVS     r1,#0                 ;114
0000b2  2008              MOVS     r0,#8                 ;114
0000b4  e7e6              B        |L5.132|
;;;118    
                          ENDP
0000b6  0000              DCW      0x0000
                  |L5.184|
                          DCD      0x40020100
                  |L5.188|
                          DCD      0x40021100
                          AREA ||i.TIM_GetAutoreload||, CODE, READONLY, ALIGN=1
                  TIM_GetAutoreload PROC
;;;316     */
;;;317    uint16_t TIM_GetAutoreload ( TIM_TypeDef* TIMx )
000000  6880              LDR      r0,[r0,#8]
;;;318    {
;;;319        
;;;320        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;321    
;;;322        
;;;323        return TIMx->TIM_RLD;
000002  b280              UXTH     r0,r0
;;;324    }
000004  4770              BX       lr
;;;325    
                          ENDP
                          AREA ||i.TIM_GetCounter||, CODE, READONLY, ALIGN=1
                  TIM_GetCounter PROC
;;;263     */
;;;264    uint32_t TIM_GetCounter ( TIM_TypeDef* TIMx )
000000  6840              LDR      r0,[r0,#4]
;;;265    {
;;;266        
;;;267        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;268    
;;;269        
;;;270        return TIMx->TIM_CNT;
;;;271    }
000002  4770              BX       lr
;;;272    
                          ENDP
                          AREA ||i.TIM_GetFailingCapture||, CODE, READONLY, ALIGN=1
                  TIM_GetFailingCapture PROC
;;;570      */
;;;571    uint32_t TIM_GetFailingCapture ( TIM_TypeDef* TIMx )
000000  6940              LDR      r0,[r0,#0x14]
;;;572    {
;;;573        
;;;574        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;575    
;;;576        
;;;577        return TIMx->TIM_PDTB_FCAP;
;;;578    }
000002  4770              BX       lr
;;;579    
                          ENDP
                          AREA ||i.TIM_GetFlagStatus||, CODE, READONLY, ALIGN=1
                  TIM_GetFlagStatus PROC
;;;956     */
;;;957    FlagStatus TIM_GetFlagStatus ( TIM_TypeDef* TIMx, TIM_Flag_TypeDef TIM_FLAG )
000000  4602              MOV      r2,r0
;;;958    {
;;;959        FlagStatus bitstatus = RESET;
;;;960        
;;;961        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;962        assert_param ( IS_GET_TIM_FLAG ( TIM_FLAG ) );
;;;963    
;;;964        if ( ( TIMx->TIM_STS & TIM_FLAG ) != ( uint16_t ) RESET )
000002  68d2              LDR      r2,[r2,#0xc]
000004  2000              MOVS     r0,#0                 ;959
000006  420a              TST      r2,r1
000008  d000              BEQ      |L9.12|
;;;965        {
;;;966            bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L9.12|
;;;967        }
;;;968        else
;;;969        {
;;;970            bitstatus = RESET;
;;;971        }
;;;972        return bitstatus;
;;;973    }
00000c  4770              BX       lr
;;;974    
                          ENDP
                          AREA ||i.TIM_GetPrescaler||, CODE, READONLY, ALIGN=1
                  TIM_GetPrescaler PROC
;;;390     */
;;;391    TIM_Prescaler_TypeDef TIM_GetPrescaler ( TIM_TypeDef* TIMx )
000000  6800              LDR      r0,[r0,#0]
;;;392    {
;;;393        
;;;394        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;395    
;;;396        
;;;397        return ( TIM_Prescaler_TypeDef ) ( TIMx->TIM_CON & TIM_CON_TIMCLK );
000002  2107              MOVS     r1,#7
000004  0209              LSLS     r1,r1,#8
000006  4008              ANDS     r0,r0,r1
;;;398    }
000008  4770              BX       lr
;;;399    
                          ENDP
                          AREA ||i.TIM_GetRisingCapture||, CODE, READONLY, ALIGN=1
                  TIM_GetRisingCapture PROC
;;;544      */
;;;545    uint32_t TIM_GetRisingCapture ( TIM_TypeDef* TIMx )
000000  6900              LDR      r0,[r0,#0x10]
;;;546    {
;;;547        
;;;548        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;549    
;;;550        
;;;551        return TIMx->TIM_PDTA_RCAP;
;;;552    }
000002  4770              BX       lr
;;;553    
                          ENDP
                          AREA ||i.TIM_ICCmd||, CODE, READONLY, ALIGN=2
                  TIM_ICCmd PROC
;;;509     */
;;;510    void TIM_ICCmd ( TIM_TypeDef* TIMx, FunctionalState NewState )
000000  2900              CMP      r1,#0
;;;511    {
;;;512        
;;;513        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;514        assert_param ( IS_FUNCTIONAL_STATE ( NewState ) );
;;;515    
;;;516        if ( NewState != DISABLE )
;;;517        {
;;;518            
;;;519            TIMx->TIM_CON |= TIM_CON_CPRL;
;;;520        }
;;;521        else
;;;522        {
;;;523            
;;;524            TIMx->TIM_CON &= ( uint16_t ) ~TIM_CON_CPRL;
000002  6801              LDR      r1,[r0,#0]
000004  d002              BEQ      |L12.12|
000006  2201              MOVS     r2,#1                 ;519
000008  4311              ORRS     r1,r1,r2              ;519
00000a  e001              B        |L12.16|
                  |L12.12|
00000c  4a01              LDR      r2,|L12.20|
00000e  4011              ANDS     r1,r1,r2
                  |L12.16|
000010  6001              STR      r1,[r0,#0]            ;519
;;;525        }
;;;526    }
000012  4770              BX       lr
;;;527    
                          ENDP
                  |L12.20|
                          DCD      0x0000fffe
                          AREA ||i.TIM_ICInit||, CODE, READONLY, ALIGN=1
                  TIM_ICInit PROC
;;;432     */
;;;433    void TIM_ICInit ( TIM_TypeDef* TIMx, TIM_IC_InitTypeDef* TIM_IC_InitStruct )
000000  b510              PUSH     {r4,lr}
;;;434    {
;;;435        uint16_t tmpreg;
;;;436        
;;;437    
;;;438    #if defined(SC32f10xx) || defined(SC32f12xx)
;;;439        if ( TIM_IC_InitStruct->TIM_FICPIN == TIM_FICPin_TnEx )
000002  884a              LDRH     r2,[r1,#2]
;;;440            assert_param ( IS_TIM_TNEX_PERIPH ( TIMx ) );
;;;441        if ( ( TIM_IC_InitStruct->TIM_FICPIN == TIM_FICPin_Tn ) ||
;;;442                ( TIM_IC_InitStruct->TIM_RICPIN == TIM_RICPin_Tn ) )
000004  880b              LDRH     r3,[r1,#0]
;;;443            assert_param ( IS_TIM_TN_PERIPH ( TIMx ) );
;;;444    #elif defined(SC32f11xx)|| defined(SC32f15xx)
;;;445        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;446    #endif
;;;447    
;;;448    
;;;449        
;;;450        tmpreg = ( uint16_t ) TIMx->TIM_CON;
000006  6801              LDR      r1,[r0,#0]
;;;451    
;;;452        
;;;453        tmpreg &= ~ ( TIM_CON_EXENR | TIM_CON_EXENF | TIM_CON_FSEL | TIM_CON_EXENX );
000008  243c              MOVS     r4,#0x3c
00000a  b289              UXTH     r1,r1                 ;450
00000c  43a1              BICS     r1,r1,r4
;;;454    
;;;455    
;;;456    #if defined(SC32f10xx)
;;;457        if ( TIMx == TIM0 )
;;;458        {
;;;459            if ( TIM_IC_InitStruct->TIM_FICPIN != TIM_FICPin_Tn )
;;;460            {
;;;461                tmpreg |= TIM_IC_InitStruct->TIM_FICPIN;
;;;462            }
;;;463    
;;;464        }
;;;465        else
;;;466        {
;;;467            tmpreg |= ( TIM_IC_InitStruct->TIM_FICPIN | TIM_IC_InitStruct->TIM_RICPIN );
;;;468        }
;;;469    #elif defined(SC32f11xx) || defined(SC32f12xx) ||defined(SC32f15xx)
;;;470    
;;;471        tmpreg |= ( TIM_IC_InitStruct->TIM_FICPIN | TIM_IC_InitStruct->TIM_RICPIN );
00000e  431a              ORRS     r2,r2,r3
000010  430a              ORRS     r2,r2,r1
;;;472    #endif
;;;473    
;;;474    
;;;475        TIMx->TIM_CON = ( uint32_t ) tmpreg;
000012  6002              STR      r2,[r0,#0]
;;;476    }
000014  bd10              POP      {r4,pc}
;;;477    
                          ENDP
                          AREA ||i.TIM_ICStructInit||, CODE, READONLY, ALIGN=1
                  TIM_ICStructInit PROC
;;;482      */
;;;483    void TIM_ICStructInit ( TIM_IC_InitTypeDef* TIM_IC_InitStruct )
000000  2100              MOVS     r1,#0
;;;484    {
;;;485        
;;;486        TIM_IC_InitStruct->TIM_FICPIN = TIM_FICPin_Disable;
000002  8041              STRH     r1,[r0,#2]
;;;487        TIM_IC_InitStruct->TIM_RICPIN = TIM_RICPin_Disable;
000004  8001              STRH     r1,[r0,#0]
;;;488    }
000006  4770              BX       lr
;;;489    
                          ENDP
                          AREA ||i.TIM_ITConfig||, CODE, READONLY, ALIGN=1
                  TIM_ITConfig PROC
;;;914     */
;;;915    void TIM_ITConfig ( TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState )
000000  2a00              CMP      r2,#0
;;;916    {
;;;917        
;;;918        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;919        assert_param ( IS_TIM_IT ( TIM_IT ) );
;;;920        assert_param ( IS_FUNCTIONAL_STATE ( NewState ) );
;;;921    
;;;922        if ( NewState != DISABLE )
;;;923        {
;;;924            
;;;925            TIMx->TIM_IDE |= TIM_IT;
;;;926        }
;;;927        else
;;;928        {
;;;929            
;;;930            TIMx->TIM_IDE &= ( uint16_t ) ~TIM_IT;
000002  6982              LDR      r2,[r0,#0x18]
000004  d001              BEQ      |L15.10|
000006  430a              ORRS     r2,r2,r1              ;925
000008  e002              B        |L15.16|
                  |L15.10|
00000a  43c9              MVNS     r1,r1
00000c  b289              UXTH     r1,r1
00000e  400a              ANDS     r2,r2,r1
                  |L15.16|
000010  6182              STR      r2,[r0,#0x18]         ;925
;;;931        }
;;;932    }
000012  4770              BX       lr
;;;933    
                          ENDP
                          AREA ||i.TIM_PWMGetDuty||, CODE, READONLY, ALIGN=1
                  TIM_PWMGetDuty PROC
;;;751     */
;;;752    uint16_t TIM_PWMGetDuty ( TIM_TypeDef* TIMx, TIM_PWMChannel_Typedef TIM_PWMChannel )
000000  2902              CMP      r1,#2
;;;753    {
000002  d002              BEQ      |L16.10|
;;;754        uint16_t tmpduty = 0;
;;;755    
;;;756        
;;;757        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;758    
;;;759        if ( TIM_PWMChannel == TIM_PWMChannel_PWMA )
;;;760        {
;;;761            tmpduty = ( uint16_t ) TIMx->TIM_PDTA_RCAP;
;;;762        }
;;;763        else
;;;764        {
;;;765            tmpduty = ( uint16_t ) TIMx->TIM_PDTB_FCAP;
000004  6940              LDR      r0,[r0,#0x14]
                  |L16.6|
000006  b280              UXTH     r0,r0                 ;761
;;;766        }
;;;767    
;;;768        return tmpduty;
;;;769    }
000008  4770              BX       lr
                  |L16.10|
00000a  6900              LDR      r0,[r0,#0x10]         ;761
00000c  e7fb              B        |L16.6|
;;;770    
                          ENDP
                          AREA ||i.TIM_PWMInit||, CODE, READONLY, ALIGN=1
                  TIM_PWMInit PROC
;;;613     */
;;;614    void TIM_PWMInit ( TIM_TypeDef* TIMx, TIM_PWM_InitTypeDef* TIM_PWM_InitStruct )
000000  b510              PUSH     {r4,lr}
;;;615    {
;;;616        uint32_t tmpreg;
;;;617        
;;;618    #if defined(SC32f10xx) || defined(SC32f12xx)
;;;619        if ( ( TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl == TIM_PWMChannel_PWMA ) ||
000002  884a              LDRH     r2,[r1,#2]
;;;620                ( TIM_PWM_InitStruct->TIM_PWMOutputChannl == TIM_PWMChannel_PWMA ) )
000004  880b              LDRH     r3,[r1,#0]
;;;621            assert_param ( IS_TIM_TN_PERIPH ( TIMx ) );
;;;622        if ( ( TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl == TIM_PWMChannel_PWMB ) ||
;;;623                ( TIM_PWM_InitStruct->TIM_PWMOutputChannl == TIM_PWMChannel_PWMB ) )
;;;624            assert_param ( IS_TIM_TNEX_PERIPH ( TIMx ) );
;;;625    #elif defined(SC32f11xx)|| defined(SC32f15xx)
;;;626        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;627    #endif
;;;628        
;;;629        tmpreg = TIMx->TIM_CON;
000006  6801              LDR      r1,[r0,#0]
;;;630    
;;;631        
;;;632        tmpreg &= ( uint32_t ) ~ ( TIM_CON_EPWMNA | TIM_CON_EPWMNB | TIM_CON_INVNA | TIM_CON_INVNB );
000008  240f              MOVS     r4,#0xf
00000a  02e4              LSLS     r4,r4,#11
;;;633    
;;;634        
;;;635    #if defined(SC32f10xx)
;;;636        
;;;637        if ( ( ( TIMx == TIM0 ) && ( TIM_PWM_InitStruct->TIM_PWMOutputChannl != TIM_PWMChannel_PWMA ) &&
;;;638                ( TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl != TIM_PWMChannel_PWMA ) ) ||
;;;639                ( ( TIMx != TIM0 ) && ( TIM_PWM_InitStruct->TIM_PWMOutputChannl != TIM_PWMChannel_PWMB ) &&
;;;640                  ( TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl != TIM_PWMChannel_PWMB ) ) )
;;;641        {
;;;642            
;;;643            
;;;644            tmpreg |= ( uint32_t ) ( ( TIM_PWM_InitStruct->TIM_PWMOutputChannl << ( 13U ) )
;;;645                                     | ( TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl ) << ( 11U ) );
;;;646        }
;;;647    #elif defined(SC32f11xx)|| defined(SC32f12xx)|| defined(SC32f15xx)
;;;648        {
;;;649            
;;;650            
;;;651            tmpreg |= ( uint32_t ) ( ( TIM_PWM_InitStruct->TIM_PWMOutputChannl << ( 13U ) )
00000c  035b              LSLS     r3,r3,#13
00000e  02d2              LSLS     r2,r2,#11
000010  43a1              BICS     r1,r1,r4              ;632
000012  4313              ORRS     r3,r3,r2
000014  430b              ORRS     r3,r3,r1
;;;652                                     | ( TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl ) << ( 11U ) );
;;;653        }
;;;654    
;;;655    #endif
;;;656    
;;;657        
;;;658        TIMx->TIM_CON = tmpreg;
000016  6003              STR      r3,[r0,#0]
;;;659    }
000018  bd10              POP      {r4,pc}
;;;660    
                          ENDP
                          AREA ||i.TIM_PWMSetDuty||, CODE, READONLY, ALIGN=1
                  TIM_PWMSetDuty PROC
;;;694     */
;;;695    void TIM_PWMSetDuty ( TIM_TypeDef* TIMx, TIM_PWMChannel_Typedef TIM_PWMChannel, uint16_t PWM_DutyValue )
000000  2902              CMP      r1,#2
;;;696    {
000002  d003              BEQ      |L18.12|
;;;697    #if defined(SC32f10xx)
;;;698        
;;;699        if ( TIM_PWMChannel == TIM_PWMChannel_PWMA )
;;;700            assert_param ( IS_TIM_TN_PERIPH ( TIMx ) );
;;;701        if ( TIM_PWMChannel == TIM_PWMChannel_PWMB )
;;;702            assert_param ( IS_TIM_TNEX_PERIPH ( TIMx ) );
;;;703    
;;;704        
;;;705        if ( ( TIMx != TIM0 ) && ( TIM_PWMChannel == TIM_PWMChannel_PWMA ) )
;;;706        {
;;;707            TIMx->TIM_PDTA_RCAP = PWM_DutyValue;
;;;708        }
;;;709        
;;;710        else if ( ( TIMx == TIM0 ) && ( TIM_PWMChannel == TIM_PWMChannel_PWMB ) )
;;;711        {
;;;712            TIMx->TIM_PDTB_FCAP = PWM_DutyValue;
;;;713        }
;;;714    #elif defined(SC32f11xx)|| defined(SC32f12xx)|| defined(SC32f15xx)
;;;715        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;716    
;;;717        if ( TIM_PWMChannel == TIM_PWMChannel_PWMA )
;;;718        {
;;;719            TIMx->TIM_PDTA_RCAP = PWM_DutyValue;
;;;720        }
;;;721        else if ( TIM_PWMChannel == TIM_PWMChannel_PWMB )
000004  2901              CMP      r1,#1
000006  d100              BNE      |L18.10|
;;;722        {
;;;723            TIMx->TIM_PDTB_FCAP = PWM_DutyValue;
000008  6142              STR      r2,[r0,#0x14]
                  |L18.10|
;;;724        }
;;;725    
;;;726    #endif
;;;727    
;;;728    
;;;729    }
00000a  4770              BX       lr
                  |L18.12|
00000c  6102              STR      r2,[r0,#0x10]         ;719
00000e  4770              BX       lr
;;;730    
                          ENDP
                          AREA ||i.TIM_PWMStructInit||, CODE, READONLY, ALIGN=1
                  TIM_PWMStructInit PROC
;;;665      */
;;;666    void TIM_PWMStructInit ( TIM_PWM_InitTypeDef* TIM_PWM_InitStruct )
000000  2100              MOVS     r1,#0
;;;667    {
;;;668        
;;;669        TIM_PWM_InitStruct->TIM_PWMLowPolarityChannl = TIM_PWMChannel_Less;
000002  8041              STRH     r1,[r0,#2]
;;;670        TIM_PWM_InitStruct->TIM_PWMOutputChannl = TIM_PWMChannel_Less;
000004  8001              STRH     r1,[r0,#0]
;;;671    }
000006  4770              BX       lr
;;;672    
                          ENDP
                          AREA ||i.TIM_SetAutoreload||, CODE, READONLY, ALIGN=1
                  TIM_SetAutoreload PROC
;;;290     */
;;;291    void TIM_SetAutoreload ( TIM_TypeDef* TIMx, uint16_t Autoreload )
000000  6081              STR      r1,[r0,#8]
;;;292    {
;;;293        
;;;294        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;295    
;;;296        
;;;297        TIMx->TIM_RLD = Autoreload;
;;;298    }
000002  4770              BX       lr
;;;299    
                          ENDP
                          AREA ||i.TIM_SetCounter||, CODE, READONLY, ALIGN=1
                  TIM_SetCounter PROC
;;;237     */
;;;238    void TIM_SetCounter ( TIM_TypeDef* TIMx, uint32_t Counter )
000000  6041              STR      r1,[r0,#4]
;;;239    {
;;;240        
;;;241        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;242    
;;;243        
;;;244        TIMx->TIM_CNT = ( uint32_t ) Counter;
;;;245    }
000002  4770              BX       lr
;;;246    
                          ENDP
                          AREA ||i.TIM_SetPerscaler||, CODE, READONLY, ALIGN=1
                  TIM_SetPerscaler PROC
;;;351     */
;;;352    void TIM_SetPerscaler ( TIM_TypeDef* TIMx, TIM_Prescaler_TypeDef TIM_Perscaler )
000000  6802              LDR      r2,[r0,#0]
;;;353    {
;;;354    
;;;355        
;;;356        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;357        assert_param ( IS_TIM_PRESCALER ( TIM_Perscaler ) );
;;;358    
;;;359        
;;;360        TIMx->TIM_CON &= ( uint32_t ) ( ~TIM_CON_TIMCLK );
000002  2307              MOVS     r3,#7
000004  021b              LSLS     r3,r3,#8
000006  439a              BICS     r2,r2,r3
000008  6002              STR      r2,[r0,#0]
;;;361    
;;;362        
;;;363        TIMx->TIM_CON |= TIM_Perscaler;
00000a  6802              LDR      r2,[r0,#0]
00000c  430a              ORRS     r2,r2,r1
00000e  6002              STR      r2,[r0,#0]
;;;364    }
000010  4770              BX       lr
;;;365    
                          ENDP
                          AREA ||i.TIM_TIMBaseInit||, CODE, READONLY, ALIGN=2
                  TIM_TIMBaseInit PROC
;;;137     */
;;;138    void TIM_TIMBaseInit ( TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct )
000000  b530              PUSH     {r4,r5,lr}
;;;139    {
;;;140        
;;;141        uint32_t tmpreg;
;;;142        assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) );
;;;143        assert_param ( IS_TIM_PRESCALER ( TIM_TimeBaseInitStruct->TIM_EXENX ) );
;;;144        assert_param ( IS_TIM_WORKMODE ( TIM_TimeBaseInitStruct->TIM_WorkMode ) );
;;;145        assert_param ( IS_TIM_COUNTERMODE ( TIM_TimeBaseInitStruct->TIM_CounterMode ) );
;;;146        assert_param ( IS_TIM_RICPin ( TIM_TimeBaseInitStruct->TIM_Prescaler ) );
;;;147    
;;;148        
;;;149        
;;;150        tmpreg = TIMx->TIM_CON;
000002  6803              LDR      r3,[r0,#0]
;;;151        
;;;152        tmpreg &= ( uint32_t ) ~ ( TIM_CON_TIMCLK | TIM_CON_CTSEL | TIM_CON_DEC | TIM_CON_EXENX );
000004  4a07              LDR      r2,|L23.36|
;;;153        
;;;154        
;;;155        
;;;156        
;;;157        
;;;158        tmpreg |= ( uint32_t ) ( TIM_TimeBaseInitStruct->TIM_Prescaler | TIM_TimeBaseInitStruct->TIM_CounterMode |
000006  888c              LDRH     r4,[r1,#4]
000008  4013              ANDS     r3,r3,r2              ;152
00000a  880a              LDRH     r2,[r1,#0]
00000c  88cd              LDRH     r5,[r1,#6]
00000e  4322              ORRS     r2,r2,r4
000010  884c              LDRH     r4,[r1,#2]
000012  016d              LSLS     r5,r5,#5
000014  432c              ORRS     r4,r4,r5
000016  4322              ORRS     r2,r2,r4
000018  431a              ORRS     r2,r2,r3
;;;159                                 TIM_TimeBaseInitStruct->TIM_WorkMode | ( TIM_TimeBaseInitStruct->TIM_EXENX << TIM_CON_EXENX_Pos ) );
;;;160        
;;;161        TIMx->TIM_CON = tmpreg;
00001a  6002              STR      r2,[r0,#0]
;;;162        
;;;163        TIMx->TIM_CNT = TIMx->TIM_RLD = TIM_TimeBaseInitStruct->TIM_Preload;
00001c  8909              LDRH     r1,[r1,#8]
00001e  6081              STR      r1,[r0,#8]
000020  6041              STR      r1,[r0,#4]
;;;164    
;;;165    }
000022  bd30              POP      {r4,r5,pc}
;;;166    
                          ENDP
                  |L23.36|
                          DCD      0xfffff89d
                          AREA ||i.TIM_TimeBaseStructInit||, CODE, READONLY, ALIGN=1
                  TIM_TimeBaseStructInit PROC
;;;171      */
;;;172    void TIM_TimeBaseStructInit ( TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct )
000000  2100              MOVS     r1,#0
;;;173    {
;;;174        
;;;175        TIM_TimeBaseInitStruct->TIM_Prescaler = TIM_PRESCALER_1;
000002  8001              STRH     r1,[r0,#0]
;;;176        TIM_TimeBaseInitStruct->TIM_WorkMode = TIM_WorkMode_Timer;
000004  8041              STRH     r1,[r0,#2]
;;;177        TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
000006  8081              STRH     r1,[r0,#4]
;;;178        TIM_TimeBaseInitStruct->TIM_Preload = 0x0000;
000008  8101              STRH     r1,[r0,#8]
;;;179        TIM_TimeBaseInitStruct->TIM_EXENX = TIM_EXENX_Disable;
00000a  80c1              STRH     r1,[r0,#6]
;;;180    }
00000c  4770              BX       lr
;;;181    
                          ENDP
;*** Start embedded assembler ***
#line 1 "..\\FWLib\\SC32F1XXX_Lib\\src\\sc32f1xxx_tim.c"
	AREA ||.rev16_text||, CODE
	THUMB
	EXPORT |__asm___15_sc32f1xxx_tim_c_c458916b____REV16|
#line 463 "..\\CMSIS\\cmsis_armcc.h"
|__asm___15_sc32f1xxx_tim_c_c458916b____REV16| PROC
#line 464
 rev16 r0, r0
 bx lr
	ENDP
	AREA ||.revsh_text||, CODE
	THUMB
	EXPORT |__asm___15_sc32f1xxx_tim_c_c458916b____REVSH|
#line 478
|__asm___15_sc32f1xxx_tim_c_c458916b____REVSH| PROC
#line 479
 revsh r0, r0
 bx lr
	ENDP
;*** End   embedded assembler ***
